


module bus_led(
    input clk , 
    input rst_n , 

    input  wire [7:0]  m_dat_i  , 
    output wire [7:0]  m_dat_o  , 
    input  wire [7:0]  m_adr_i , 
    input  wire        m_wen_i  ,

    output reg [7:0]   led 
) ;


always @(posedge clk ) begin
    if(~rst_n) begin
        led <= 8'h0 ;
    end else begin
        if(m_wen_i) begin
            case(m_adr_i)
                8'h00: begin 
                    led <= m_dat_i ;
                    $display("%t ns | led=%d" , $time , m_dat_i) ;
                end 
            endcase 
        end
    end
end

assign m_dat_o = led ;

endmodule 

